Actually I was, CISC and RISC are both Von Neumann machines. ISA has more to do with encoding these days anyway. Basically, despite how sophisticated the CPU o

Actually I was, CISC and RISC are both Von Neumann machines. ISA has more to do with encoding these days anyway. Basically, despite how sophisticated the CPU of these machines becomes it is still trying to make the appearance of executing instructions in sequence. Current x86 processors can execute many instructions in parallel under the correct conditions leading to Instructions Per Clock (IPC) greater much than one. However typical IPC hovers around 1 and some change, unless a lot of optimization effort is invested. In order execution of an instruction sequence (or the appearance to the user of it) is the bottleneck that has led to single threaded CPU speed increases to all but disappear now that CPU frequency scaling has more or less halted.