3 ms·
There are no cacheline-size store instructions pre AVX-512 (on Ivybridge, the widest store is 32B, and even that cracks to two 16B store uops; it's a real 32B s
by stephencanon 9y ago
There are no cacheline-size store instructions pre AVX-512 (on Ivybridge, the widest store is 32B, and even that cracks to two 16B store uops; it's a real 32B store on Haswell+). Also the NT stores suffer from a bunch of other hazards that rep/movs avoids.
- gpderetta 9y agoNon temporal stores shouldn't go to the cache at all though. They go to write combining buffers instead.
- stephencanon 9y agoShouldn't, but do. They RFO into the LLC.