6 ms·

IBM’s world-first 5nm chip indicates EUV lithography is ready for primetime

114 points by rbii 9y ago

elorant 9y ago
So, what happens when we reach 1nm? Can we go even lower or we'd need a paradigm shift?
- gbrown_ 9y ago
  We're not likely to get below 3nm. We getting into the realm of making things on a feature set of a handful of atoms. It's insane we've got this far. Then there's the matter of using this for production of large scale shipping chips. Note the POWER9 (IBM's next big chip) is expected to be produced on 14nm. > we'd need a paradigm shift? Yes we're coming to the end of the road for traditional CMOS chips. I don't think anyone really knows what's next as there's no clear successor. I would speculate in the coming years we'll be seeing more performance coming from invocations in the data path for general purpose computing. Of course exploitation of massive parallelism will continue.
  - hyperpallium 9y ago
    14nm? Wait, isn't the iPhone 8's A11 to be on 10nm? I can't imagine TSMC being ahead of IBM's foundry, so what's going on here? Non-technical "nm"?
    - tormeh 9y ago
      Coarser processes have their benefits, especially when they've matured for a while. When you're building a large chip you start really thinking about yield. Coarser and more mature processes give better yield. I would assume that maximum yield would be achieved by very accurate machinery making coarse chips, like using 14nm lithography to make 22nm chips, but this is rarely done in practice, I think.
    - Someone 9y ago
      http://spectrum.ieee.org/semiconductors/devices/the-status-of-moores-law-its-complicated http://spectrum.ieee.org/semiconductors/devices/the-status-o...: "The company’s 0.13-µm chips, which debuted in 2001, had transistor gates that were actually just 70 nm long. [...] Through all this, node name numbers continued to drift ever downward, and the density of transistors continued to double from generation to generation. But the names no longer match the size of any specific chip dimension. “The minimum dimensions are getting smaller,” Bohr says. “But I’m the first to admit that I can’t point to the one dimension that’s 32 nm or 22 nm or 14 nm. Some dimensions are smaller than the stated node name, and others are larger.” The switch to FinFETs has made the situation even more complex. Bohr points out, for example, that Intel’s 22-nm chips, the current state of the art, have FinFET transistors with gates that are 35 nm long but fins that are just 8 nm wide." If there wasn't such an enormous difference between the two, I bet some foundries would have silently started reporting transistor sizes in nautical miles (nm) in order to ensure the number kept decreasing.
- kowdermeister 9y ago
  Most likely, yes: Using light: http://gizmodo.com/a-new-light-based-transistor-could-completely-change-th-1756798032 http://gizmodo.com/a-new-light-based-transistor-could-comple... Building on memristors: http://www.memristor.org/reference/research/13/what-are-memristors http://www.memristor.org/reference/research/13/what-are-memr... http://spectrum.ieee.org/semiconductors/design/the-mysterious-memristor http://spectrum.ieee.org/semiconductors/design/the-mysteriou... Neural network inspiried chips: http://www.research.ibm.com/articles/brain-chip.shtml http://www.research.ibm.com/articles/brain-chip.shtml I think we will see some breakthrough after the CPU industry goes into an existential crisis about going below 5nm. Current pipelines are just so damn expensive to replace that we will see gradual innovations. For example TPU-s[1] might be a standard in a few years like GPU-s are now. The current trends are clearly in reducing power usage and size. That alone will be a huge innovation when I can hold a "server farm" in my pocket. [1] https://cloud.google.com/tpu/ https://cloud.google.com/tpu/
  - mstresh 9y ago
    About using light: I don't believe light will replace the transistors performing logic except in a few niche applications (e.g. [1]). Light is physically constrained by it's wavelength. It's difficult to build interacting structures smaller than a few hundred nm and it's difficult to build light-generating elements with even shorter wavelengths--you're approaching the Deep UV and X-rays. Maybe you can get to the tens to low hundreds of nm with plasmonics, but this is still far from the realm in which it makes sense to replace an electronic transistor with an optical transistor. Furthermore, it's also difficult to achieve strong nonlinearities in optical systems, especially silicon. You need some sort of nonlinear element for switching. Light-based communication probably will replace certain I/O blocks on chip. These tend to be quite large in terms of area after considering power and ESD constraints. [1] Discussion here: https://news.ycombinator.com/item?id=13051984 https://news.ycombinator.com/item?id=13051984
    - kowdermeister 9y ago
      It's not a goal I guess to shrink these "photon CPU-s" to 5nm at start. > but this is still far from the realm in which it makes sense to replace an electronic transistor with an optical transistor The electromagnetic spectrum even at mid-near infrared wavelengths frequencies could help chips operate on the THz scale! You might list a mountain of reasons it can't work, but it's just fun to imagine that it might be possible to turn a cycle of light to an operation. You can build interesting things at that scale, in this research they also refer to communication as you mentioned [1] Thanks for that link, I downloaded the paper :) [1] http://newscenter.lbl.gov/2011/05/31/nanoscale-waveguide-for-future-photonics/ http://newscenter.lbl.gov/2011/05/31/nanoscale-waveguide-for...
- anthonybsd 9y ago
  I strongly doubt we can even reach 1nm on a mass scale. Quantum tunneling will mess with that quite a bit: https://www.quora.com/What-is-Quantum-Tunneling-Limit-How-does-it-limit-the-size-of-a-transistor https://www.quora.com/What-is-Quantum-Tunneling-Limit-How-do...
- igravious 9y ago
  1nm isn't a special number just because it is 1. A nm is one billionth of a metre which itself is an arbitrary length so 1nm is a purely arbitrary cut-off. What you should be asking is how many molecules of silicon and silicon-germanium can be packed into the spaces being talked about at the different fabrication levels of 14nm, 10nm, 7nm, 5nm, and so on. Once you have that information then you can ask what is the smallest number of molecules that these processes can scale down to. Only then we can start asking about physical limits and more exotic processes. Are we talking about features of 50 or 40 molecules across or what? All I know is that 1nm is not a magic number and that predictions about the demise of transistor scaling have always turned out to be wrong. My prediction is that, as unimaginable as it seems, we'll be able to scale down to the physical limits of the materials.
  - ant6n 9y ago
    > we'll be able to scale down to the physical limits of the materials. So that's like 1nm?
    - halomru 9y ago
      Somewhere between 0.1nm and 1nm.
  - b34r 9y ago
    According to my very unscientific googling, a silicon atom is approximately 111 picometers, or just over 1/10 of a nanometer. So if we can make stable gates with only 3-4 Si atoms, we can definitely go below 1nm.
    - snovv_crash 9y ago
      Don't forget you need a doping atom as well.
  - davidiach 9y ago
    >All I know is that 1nm is not a magic number and that predictions about the demise of transistor scaling have always turned out to be wrong. My prediction is that, as unimaginable as it seems, we'll be able to scale down to the physical limits of the materials. This is very important to be pointed out. The burden of proof should be on the people who suggest that "this time it is different", not on those who correctly assumed that technology tends to progress in time.
- dbcooper 9y ago
  Node names used to refer to transistor gate length, but now they're pretty arbitrary, and gate length is typically 2x or more than node name. The "1nm" node would still have very small feature sizes though.
whazor 9y ago
> EUV has been waiting in the wings for about 10 years now, always just a few months away from commercial viability. This is the best sign yet that ASML's EUV tech is finally ready for primetime. This is the real message, because creating 5nm chips was already possible[1]. However, creating them massively on scale with the ASML EUV machines is the real challenge. [1] https://www.semiwiki.com/forum/content/5080-imec-cadence-disclose-5nm-test-chip.html https://www.semiwiki.com/forum/content/5080-imec-cadence-dis...
- davidf18 9y ago
  It is possible/probable that these processes are used by NSA/DARPA, military applications. In many of these situations performance well trumps volume/cost issues.
  - Nokinside 9y ago
    Not really. NSA/DARPA have no need for small batches of very expensive circuits manufactured with 5 nm. They need large volumes of cost effective processors as well. Manufacturing their own special purpose asics with older technology is more likely.
kurthr 9y ago
I wish this wasn't so laughable. What this really shows is that IBM has high margins for their chips, and a long standing tolerance for absurdly low yields and long wafer turn times. That they announce "production" before any of the other fabs is more likely do to PR needs than real technical advancement. https://arstechnica.com/gadgets/2015/07/ibm-unveils-industrys-first-7nm-chip-moving-beyond-silicon/ https://arstechnica.com/gadgets/2015/07/ibm-unveils-industry... EUV has been available for years and no doubt TSMC and SS have their own EUV test chips at 7nm (comparable to Intel 10nm), but the EUV equipment business will be validated by large orders and $ spent, not on prototype silicon. We aren't there yet (but probably will be in a year or so- they've gone from 100W to 150W in the last 9months and need to hit 200-250W). Will we have 1-3nm transistors? Yes. Will they be commercially viable? Probably No. Moore's law ends when the CFOs decide it's not worth building another multi-$B factory on schedule based on net expected return... which already happened over the last 4 years. Sorry, downvote at will.
- deleted 9y ago
  [deleted]
- undersuit 9y ago
  >Will we have 1-3nm transistors? Yes. Will they be commercially viable? Probably No. Why not? We can only stack our layers so much, eventually the 1-3nm range of transistors will become useful to give technology another squeeze before having to learn how to layer a bizarre number of layers.
  - microcolonel 9y ago
    28nm is still more expensive today than 40nm ever was, twice as expensive, per wafer, as 40nm currently is. The size of the elements is still somewhat decreasing, but the price per transistor is actually increasing at this point.
  - kurthr 9y ago
    Although there is hope that EUV will help control design rules, the current expectation for developing a 10nm design is in the $200M range. It's expected to double at 7nm and again at 5nm. Try amortizing that over anything but an iPhone, Samsung, or PC volumes.

114 points by rbii 9y ago

elorant 9y ago

So, what happens when we reach 1nm? Can we go even lower or we'd need a paradigm shift?

gbrown_ 9y ago
We're not likely to get below 3nm. We getting into the realm of making things on a feature set of a handful of atoms. It's insane we've got this far. Then there's the matter of using this for production of large scale shipping chips. Note the POWER9 (IBM's next big chip) is expected to be produced on 14nm. > we'd need a paradigm shift? Yes we're coming to the end of the road for traditional CMOS chips. I don't think anyone really knows what's next as there's no clear successor. I would speculate in the coming years we'll be seeing more performance coming from invocations in the data path for general purpose computing. Of course exploitation of massive parallelism will continue.
- hyperpallium 9y ago
  14nm? Wait, isn't the iPhone 8's A11 to be on 10nm? I can't imagine TSMC being ahead of IBM's foundry, so what's going on here? Non-technical "nm"?
  - tormeh 9y ago
    Coarser processes have their benefits, especially when they've matured for a while. When you're building a large chip you start really thinking about yield. Coarser and more mature processes give better yield. I would assume that maximum yield would be achieved by very accurate machinery making coarse chips, like using 14nm lithography to make 22nm chips, but this is rarely done in practice, I think.
  - Someone 9y ago
    http://spectrum.ieee.org/semiconductors/devices/the-status-of-moores-law-its-complicated http://spectrum.ieee.org/semiconductors/devices/the-status-o...: "The company’s 0.13-µm chips, which debuted in 2001, had transistor gates that were actually just 70 nm long. [...] Through all this, node name numbers continued to drift ever downward, and the density of transistors continued to double from generation to generation. But the names no longer match the size of any specific chip dimension. “The minimum dimensions are getting smaller,” Bohr says. “But I’m the first to admit that I can’t point to the one dimension that’s 32 nm or 22 nm or 14 nm. Some dimensions are smaller than the stated node name, and others are larger.” The switch to FinFETs has made the situation even more complex. Bohr points out, for example, that Intel’s 22-nm chips, the current state of the art, have FinFET transistors with gates that are 35 nm long but fins that are just 8 nm wide." If there wasn't such an enormous difference between the two, I bet some foundries would have silently started reporting transistor sizes in nautical miles (nm) in order to ensure the number kept decreasing.
kowdermeister 9y ago
Most likely, yes: Using light: http://gizmodo.com/a-new-light-based-transistor-could-completely-change-th-1756798032 http://gizmodo.com/a-new-light-based-transistor-could-comple... Building on memristors: http://www.memristor.org/reference/research/13/what-are-memristors http://www.memristor.org/reference/research/13/what-are-memr... http://spectrum.ieee.org/semiconductors/design/the-mysterious-memristor http://spectrum.ieee.org/semiconductors/design/the-mysteriou... Neural network inspiried chips: http://www.research.ibm.com/articles/brain-chip.shtml http://www.research.ibm.com/articles/brain-chip.shtml I think we will see some breakthrough after the CPU industry goes into an existential crisis about going below 5nm. Current pipelines are just so damn expensive to replace that we will see gradual innovations. For example TPU-s[1] might be a standard in a few years like GPU-s are now. The current trends are clearly in reducing power usage and size. That alone will be a huge innovation when I can hold a "server farm" in my pocket. [1] https://cloud.google.com/tpu/ https://cloud.google.com/tpu/
- mstresh 9y ago
  About using light: I don't believe light will replace the transistors performing logic except in a few niche applications (e.g. [1]). Light is physically constrained by it's wavelength. It's difficult to build interacting structures smaller than a few hundred nm and it's difficult to build light-generating elements with even shorter wavelengths--you're approaching the Deep UV and X-rays. Maybe you can get to the tens to low hundreds of nm with plasmonics, but this is still far from the realm in which it makes sense to replace an electronic transistor with an optical transistor. Furthermore, it's also difficult to achieve strong nonlinearities in optical systems, especially silicon. You need some sort of nonlinear element for switching. Light-based communication probably will replace certain I/O blocks on chip. These tend to be quite large in terms of area after considering power and ESD constraints. [1] Discussion here: https://news.ycombinator.com/item?id=13051984 https://news.ycombinator.com/item?id=13051984
  - kowdermeister 9y ago
    It's not a goal I guess to shrink these "photon CPU-s" to 5nm at start. > but this is still far from the realm in which it makes sense to replace an electronic transistor with an optical transistor The electromagnetic spectrum even at mid-near infrared wavelengths frequencies could help chips operate on the THz scale! You might list a mountain of reasons it can't work, but it's just fun to imagine that it might be possible to turn a cycle of light to an operation. You can build interesting things at that scale, in this research they also refer to communication as you mentioned [1] Thanks for that link, I downloaded the paper :) [1] http://newscenter.lbl.gov/2011/05/31/nanoscale-waveguide-for-future-photonics/ http://newscenter.lbl.gov/2011/05/31/nanoscale-waveguide-for...
anthonybsd 9y ago
I strongly doubt we can even reach 1nm on a mass scale. Quantum tunneling will mess with that quite a bit: https://www.quora.com/What-is-Quantum-Tunneling-Limit-How-does-it-limit-the-size-of-a-transistor https://www.quora.com/What-is-Quantum-Tunneling-Limit-How-do...
igravious 9y ago
1nm isn't a special number just because it is 1. A nm is one billionth of a metre which itself is an arbitrary length so 1nm is a purely arbitrary cut-off. What you should be asking is how many molecules of silicon and silicon-germanium can be packed into the spaces being talked about at the different fabrication levels of 14nm, 10nm, 7nm, 5nm, and so on. Once you have that information then you can ask what is the smallest number of molecules that these processes can scale down to. Only then we can start asking about physical limits and more exotic processes. Are we talking about features of 50 or 40 molecules across or what? All I know is that 1nm is not a magic number and that predictions about the demise of transistor scaling have always turned out to be wrong. My prediction is that, as unimaginable as it seems, we'll be able to scale down to the physical limits of the materials.
- ant6n 9y ago
  > we'll be able to scale down to the physical limits of the materials. So that's like 1nm?
  - halomru 9y ago
    Somewhere between 0.1nm and 1nm.
- b34r 9y ago
  According to my very unscientific googling, a silicon atom is approximately 111 picometers, or just over 1/10 of a nanometer. So if we can make stable gates with only 3-4 Si atoms, we can definitely go below 1nm.
  - snovv_crash 9y ago
    Don't forget you need a doping atom as well.
- davidiach 9y ago
  >All I know is that 1nm is not a magic number and that predictions about the demise of transistor scaling have always turned out to be wrong. My prediction is that, as unimaginable as it seems, we'll be able to scale down to the physical limits of the materials. This is very important to be pointed out. The burden of proof should be on the people who suggest that "this time it is different", not on those who correctly assumed that technology tends to progress in time.
dbcooper 9y ago
Node names used to refer to transistor gate length, but now they're pretty arbitrary, and gate length is typically 2x or more than node name. The "1nm" node would still have very small feature sizes though.

whazor 9y ago

> EUV has been waiting in the wings for about 10 years now, always just a few months away from commercial viability. This is the best sign yet that ASML's EUV tech is finally ready for primetime. This is the real message, because creating 5nm chips was already possible[1]. However, creating them massively on scale with the ASML EUV machines is the real challenge. [1] https://www.semiwiki.com/forum/content/5080-imec-cadence-disclose-5nm-test-chip.html https://www.semiwiki.com/forum/content/5080-imec-cadence-dis...

davidf18 9y ago
It is possible/probable that these processes are used by NSA/DARPA, military applications. In many of these situations performance well trumps volume/cost issues.
- Nokinside 9y ago
  Not really. NSA/DARPA have no need for small batches of very expensive circuits manufactured with 5 nm. They need large volumes of cost effective processors as well. Manufacturing their own special purpose asics with older technology is more likely.

kurthr 9y ago

I wish this wasn't so laughable. What this really shows is that IBM has high margins for their chips, and a long standing tolerance for absurdly low yields and long wafer turn times. That they announce "production" before any of the other fabs is more likely do to PR needs than real technical advancement. https://arstechnica.com/gadgets/2015/07/ibm-unveils-industrys-first-7nm-chip-moving-beyond-silicon/ https://arstechnica.com/gadgets/2015/07/ibm-unveils-industry... EUV has been available for years and no doubt TSMC and SS have their own EUV test chips at 7nm (comparable to Intel 10nm), but the EUV equipment business will be validated by large orders and $ spent, not on prototype silicon. We aren't there yet (but probably will be in a year or so- they've gone from 100W to 150W in the last 9months and need to hit 200-250W). Will we have 1-3nm transistors? Yes. Will they be commercially viable? Probably No. Moore's law ends when the CFOs decide it's not worth building another multi-$B factory on schedule based on net expected return... which already happened over the last 4 years. Sorry, downvote at will.

deleted 9y ago
[deleted]
undersuit 9y ago
>Will we have 1-3nm transistors? Yes. Will they be commercially viable? Probably No. Why not? We can only stack our layers so much, eventually the 1-3nm range of transistors will become useful to give technology another squeeze before having to learn how to layer a bizarre number of layers.
- microcolonel 9y ago
  28nm is still more expensive today than 40nm ever was, twice as expensive, per wafer, as 40nm currently is. The size of the elements is still somewhat decreasing, but the price per transistor is actually increasing at this point.
- kurthr 9y ago
  Although there is hope that EUV will help control design rules, the current expectation for developing a 10nm design is in the $200M range. It's expected to double at 7nm and again at 5nm. Try amortizing that over anything but an iPhone, Samsung, or PC volumes.