3 ms·

In a word, empirically. In a few more words, empirically and reading a ton of Intel, AMD and VIA documentation and I'd posit, some of the patent and academic li

• tmccrmck 9y ago
  He explains his method in Instruction Tables [1] under 'How the values were measured' section and he even includes a zip of the code. I found this part particularly interesting: > It is not possible to measure the latency of a memory read or write instruction with software methods. It is only possible to measure the combined latency of a memory write followed by a memory read from the same address. What is measured here is not actually the cache access time, because in most cases the microprocessor is smart enough to make a "store forwarding" directly from the write unit to the read unit rather than waiting for the data to go to the cache and back again. The latency of this store forwarding process is arbitrarily divided into a write latency and a read latency in the tables. But in fact, the only value that makes sense to performance optimization is the sum of the write time and the read time. [1] http://www.agner.org/optimize/instruction_tables.pdf http://www.agner.org/optimize/instruction_tables.pdf