3 ms·
Less well known, but Torbjorn Granlund Instruction latencies and throughput for AMD and Intel x86 processors has also been updated for Ryzen. https://gmplib.or
by CalChris 9y ago
Less well known, but Torbjorn Granlund Instruction latencies and throughput for AMD and Intel x86 processors has also been updated for Ryzen.
https://gmplib.org/~tege/x86-timing.pdf https://gmplib.org/~tege/x86-timing.pdf
- glangdale 9y agoI hadn't seen this before, but it looks a lot like it's less well known largely because it's very incomplete (almost no SIMD) and redundant with Agner Fog's work and InstLat.
- CalChris 9y agoIt concentrates on integer ops and leaves out branches altogether. The Intel Optimization manual is pretty light on indirect branches as well. What I like about it is that it makes it easy to compare how microarchitectures handle a given instruction over time. For example, the BT instructions were a little slow, 2 cycles, 1 port through Haswell. With Broadwell that changed to 1 cycle and 2 ports. Similarly, CMOV improved with Broadwell (remember Linus' rant about the evils of CMOV?) and is now 1 cycle latency. I don't know InstLat. Do you have a link?
- mulvya 9y agohttp://instlatx64.atw.hu/ http://instlatx64.atw.hu/