3 ms·
The cache works with virtual addresses but the memory with real addresse, so when there is a cache miss and memory is accessed, the translation is done. Extra
by mhkool 9y ago
The cache works with virtual addresses but the memory with real addresse, so when there is a cache miss and memory is accessed, the translation is done. Extra bits per cache byte is nothing new: CPUs already have ECC bits.
Explaining Mach 3 is not easy in a few sentences since it is based on a few new concepts so I recommend to see the video to learn about it.
- deepnotderp 9y agoI've watched the video several times and conferred with a few people familiar with Denver. It's quite similar to a skewed pipe, why do you say it's anything different?
- mhkool 9y agoI am not familiar with skewed pipes, but nonetheless the properties of the belt and the special Mill instructions like retire gives the opportunity for a new class of pipelining not seen before and with a 3 times higher IPC.
- deepnotderp 9y agoThe belt is indeed interesting, but note that it precludes OoO should they choose to add it at a later time. I'm not entirely optimistic about the belt because basically the same thing exists on the Mali gpu (albeit not publicly documented to the best of my knowledge) and it suffers from saturation issues. The issue with ilp extraction for VLIW compilers has historically been the difficulty of drawing accurate traces through branches to get sufficient ilp. Nothing the mill has shown so far addresses this.
- mhkool 9y agotime will tell :-)