14 ms·

An issue that's not mentioned is memory consistency. It's not something that's going to solve without $$, and may pose a serious economical obstacle. EDIT: coh

• jackyinger 9y ago
  RISC-V is just an ISA, which can be thought of a s a very low level API. The memory (and most other subsystems') architecture is not tied to the ISA. Rather it has to do with load/store instruction implementation and cache organization.
  • topspin 9y ago
    "RISC-V is just an ISA" tgragnato wasn't clear enough to be certain about what he/she has in mind, but the RISC-V ISA specification -- as presently written -- has been shown to have memory consistency flaws. This emerged in April when Princeton published their TriCheck findings. RISC-V foundation has since responded by promising revisions to the ISA specification to close the holes. https://www.electronicsweekly.com/open-source-engineering/risc-v-bugs-found-princeton-2017-04/ https://www.electronicsweekly.com/open-source-engineering/ri... https://www.electronicsweekly.com/news/design/eda-and-ip/risc-v-foundation-replies-princeton-bugs-2017-04/ https://www.electronicsweekly.com/news/design/eda-and-ip/ris...
• jabl 9y ago
  They're working on a memory consistency model. Presentation from the recently concluded risc-v workshop: https://riscv.org/wp-content/uploads/2017/05/Wed1000am-Memory-Model-Lustig.pdf https://riscv.org/wp-content/uploads/2017/05/Wed1000am-Memor... (slides), https://youtu.be/E5s54AVGV2E https://youtu.be/E5s54AVGV2E (video)