5 ms·

I tried AVX512 on a Xeon (non-Phi) part recently and it was extremely underwhelming. The workload (OpenMP-parallelized n-body) was actually slower with AVX512.

I tried AVX512 on a Xeon (non-Phi) part recently and it was extremely underwhelming. The workload (OpenMP-parallelized n-body) was actually slower with AVX512. Since it was under virtualization and I didn't have access to the bare metal hardware or to performance counters, I have no way of knowing why, but I'm almost certain it was because it lost all-cores Turbo and downclocked aggressively. It had previously scaled almost linearly going from SSE to AVX/AVX2, but it regressed with AVX512.

smitherfield 9y ago
It might be your processor only supported AVX512 in emulation — the article makes it sound like only the Phi currently supports it natively.
- AbacusAvenger 9y ago
  So they implemented AVX512 on the Xeon server parts in microcode? That seems crazy.
  - smitherfield 9y ago
    It's fairly common practice with bleeding-edge vector instructions. The reasoning (assuming it is the case here) is that a theoretically-minor performance regression (the cost of converting 1x AVX512 to 2x AVX2 in microcode) is usually much preferred over a CPU exception when attempting to run a binary with AVX512 instructions on a server. It also means you don't need a $15000 chip to test your AVX512 code.
marmaduke 9y ago
That's disappointing. It may be a bad interaction between OpenMP and AVX512 (cache pressure etc)? I've also seen reliable increases in performance up through AVX2 but when I tried to run same code on a Xeon Phi, it fell short of the plain Xeon.
slizard 9y ago
What scaling are you referring to when talking about "linear"? Did you really get 2x absolute performance going from 128-bit to 256-bit SIMD (regardless of the uarch, e.g. both with SBE and HSW with the former having a relatively poor cache performance). I'd be surprised, but if your code is in the >>O(10) flops/byte regime [1] and especially friendly instruction stream too. Otherwise, I'm skeptical. Putting aside the "scaled almost linearly" statement, I'm not surprised that AVX-512 did not give the expected benefits ootb, you suddenly need double the amount of data loaded into the registers for every 512-bit instruction. You'd also quite like want to make sure masking is used effectively. [2] [1] http://people.eecs.berkeley.edu/~kubitron/cs258/lectures/lec12-Merrimac.pdf http://people.eecs.berkeley.edu/~kubitron/cs258/lectures/lec... [2] https://software.intel.com/en-us/node/523777 https://software.intel.com/en-us/node/523777

smitherfield 9y ago

It might be your processor only supported AVX512 in emulation — the article makes it sound like only the Phi currently supports it natively.

AbacusAvenger 9y ago
So they implemented AVX512 on the Xeon server parts in microcode? That seems crazy.
- smitherfield 9y ago
  It's fairly common practice with bleeding-edge vector instructions. The reasoning (assuming it is the case here) is that a theoretically-minor performance regression (the cost of converting 1x AVX512 to 2x AVX2 in microcode) is usually much preferred over a CPU exception when attempting to run a binary with AVX512 instructions on a server. It also means you don't need a $15000 chip to test your AVX512 code.

marmaduke 9y ago

That's disappointing. It may be a bad interaction between OpenMP and AVX512 (cache pressure etc)? I've also seen reliable increases in performance up through AVX2 but when I tried to run same code on a Xeon Phi, it fell short of the plain Xeon.

slizard 9y ago

What scaling are you referring to when talking about "linear"? Did you really get 2x absolute performance going from 128-bit to 256-bit SIMD (regardless of the uarch, e.g. both with SBE and HSW with the former having a relatively poor cache performance). I'd be surprised, but if your code is in the >>O(10) flops/byte regime [1] and especially friendly instruction stream too. Otherwise, I'm skeptical. Putting aside the "scaled almost linearly" statement, I'm not surprised that AVX-512 did not give the expected benefits ootb, you suddenly need double the amount of data loaded into the registers for every 512-bit instruction. You'd also quite like want to make sure masking is used effectively. [2] [1] http://people.eecs.berkeley.edu/~kubitron/cs258/lectures/lec12-Merrimac.pdf http://people.eecs.berkeley.edu/~kubitron/cs258/lectures/lec... [2] https://software.intel.com/en-us/node/523777 https://software.intel.com/en-us/node/523777