3 ms·
PC class hardware tends not to have power fail interrupts, and when power drops, and the voltage levels on the power rails start drooping, DRAM tends to go insa
by codewiz 9y ago
PC class hardware tends not to have power fail
interrupts, and when power drops, and the voltage levels on the power
rails start drooping, DRAM tends to go insane and starts returning
garbage long before the DMA engine and the hard drive stops
functioning.
This is insane, I refuse to believe it. Even a junior EE knows how to design a PCB so that the RESET signal is asserted on all ICs as soon as the voltage drops below a safe operating level.
- DannyB2 9y agoThe PCB may be well designed, but the power supply may not be. I have witnessed what a cheap PC can do. Purchased from a Walmart some years ago. Windows 7 immediately replaced with Ubuntu. After a brownout, that machine was unbootable. Also un-fsck'able. My thought was that the power supply should guarantee adequate power, or none at all. Not something in between. Also, no a rapidly alternating states of adequate power / no power. Short term solution: rebuild that system and get it a UPS. Longer term solution: get a much better box.
- tetha 9y ago> My thought was that the power supply should guarantee adequate power, or none at all. Not something in between. Also, no a rapidly alternating states of adequate power / no power. That is very hard to do, actually. Voltage does fluctuate to a certain degree, because physics. And you don't want to cut power to a system just due to a small power dip. And you can't distinguish a small power dip from 10 small power dips over some time ago. And your flapping detection only works if the power drops are close enough to each other. Proper control theory is amazingly hard. As my prof on that said - no one fully understands PID controllers, but some blokes have a really lucky thumb.
- codewiz 9y agoThe case Ted Ts'o describes is much simpler: DRAM returning garbage while the CPU is still executing instructions and sending commands on the SATA bus. This can't possibly happen even if the power supply is crazy bad, because the reset logic on the main board will halt everything before the DRAM starts malfunctioning.
- DSMan195276 9y ago> RAM returning garbage while the CPU is still executing instructions and sending commands on the SATA bus. When I read it, I got the impression he was saying the DRAM was going crazy while a DMA transfer to the hard-drive was still going on. That doesn't require the CPU to be functional when the DRAM is corrupt, only the DMA controller. I can't personally say if that makes it any more likely though.
- codewiz 9y agoThat's right, but all stateful ICs on the motherboard have a reset pin, including the north and south bridges when they were still separate packages. Even PCI cards will receive the reset signal simultaneously. Not sure what the hard drive would do with a truncated ATA command though.
- pdkl95 9y ago> SATA ext3 predates SATA, briefly. While SATA was commonly used with ext3 soon after ext3's release, a lot of the hardware Ted Ts'o is probably referring to would have been ATA-4/UDMA (or SCSI). > while the CPU is still executing instructions The problem Ts'o described doesn't involve the CPU: DRAM tends to go insane and starts returning garbage long before the DMA engine and the hard drive stops functioning. A bus-mastering ATA (or SCSI) controller - possibly on the motherboard, possibly an expansion card, regardless almost certainly PCI - may be copying data from RAM directly as Direct Memory Access. > the reset logic on the main board will halt everything In theory, there is no difference between theory and practice. In practice, there is, especially when cheap, poorly-designed hardware is involved.