> On a related note: does AMD publish block diagrams for their infinity fabric or is there any firm information about how many PCIe 3 lanes will be available o

> On a related note: does AMD publish block diagrams for their infinity fabric or is there any firm information about how many PCIe 3 lanes will be available on the Threadripper platform? I'm interested in a block diagram or documentation as well, if anyone knows of any. PcPer did some tests which show the inter-core latency and some other experimental data. https://www.pcper.com/reviews/Processors/AMD-Ryzen-and-Windows-10-Scheduler-No-Silver-Bullet https://www.pcper.com/reviews/Processors/AMD-Ryzen-and-Windo... > My understanding (please, someone tell me if I'm off base!) is that the infinity fabric is kind of like Intel's QuickPath Interconnect and the "uncore" in one. Yeah that sounds about right. The only thing I will add is that I've heard (can't source) inter-die communication on Threadripper/EPYC multi-chip-modules apparently happens by a different mechanism than intra-die/inter-CCX communication. As such, my suspicion is that Threadripper and EPYC will basically behave like a multi-socket system. As for lanes: I think it's official at this point that Threadripper has 44 lanes like Skylake-E does, and EPYC has 128 PCIe lanes. Possibly plus additional lanes from the PCH? https://arstechnica.com/gadgets/2017/05/amd-ryzen-threadripper-price-specs-release-date/ https://arstechnica.com/gadgets/2017/05/amd-ryzen-threadripp...