The specific chip in use here has two actual cores each with up to 8 hardware threads ("logical cores" in current XMOS marketing parlance). The hardware execute

The specific chip in use here has two actual cores each with up to 8 hardware threads ("logical cores" in current XMOS marketing parlance). The hardware executes instructions from the active threads in a round-robin fashion. Due to pipelining, there has to be at least 4 clock cycles between two instructions from the same thread, so maximum per-thread speed is 1/4 the overall clock speed and you can execute up to 4 threads on each core with no further slowdown. Also, the hardware cores don't share memory and communicate only via message passing, and the threads generally communicate in the same way. It's an interesting architecture which no-one's really made any use of on AmigaOne hardware for the whole 5 years it's been shipping with it.