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ARM has a system they call "big.LITTLE" which essentially works this way: each processor contains pairs of cores, one high-performance core matched up with one
by marssaxman 9y ago
ARM has a system they call "big.LITTLE" which essentially works this way: each processor contains pairs of cores, one high-performance core matched up with one low-power core, using a cache-coherent interconnect so that jobs can be swapped back and forth. They're not trying to use heterogeneous ISAs, though, so it's not quite as complicated as what you're describing.
- niftich 9y agoSamsung's Exynos 8 mixed-and-matched cores of different cache line sizes and didn't bother to make the reported cache lines be the same size. This recipe led to a hard-to-debug condition that the Mono team wrote about [1] (posted on HN [2]). [1] http://www.mono-project.com/news/2016/09/12/arm64-icache/ http://www.mono-project.com/news/2016/09/12/arm64-icache/ [2] https://news.ycombinator.com/item?id=12481700 https://news.ycombinator.com/item?id=12481700
- marssaxman 9y agoThat is an unfortunate implementation. The concept is still interesting, though.