This seems right, except that Microsoft has clearly developed a higher level language than VHDL / Verilog for writing "virtualized network functions" that compi

This seems right, except that Microsoft has clearly developed a higher level language than VHDL / Verilog for writing "virtualized network functions" that compiles down to something they can flash onto an FPGA (they call it Flow Tables in the presentation). So there's a higher level language that's, presumably, more intuitive for "normal" engineers to work with. When a new FPGA comes out the compiler is re-written and high level code stays the same. Basically the same thing we do with CPUs. So they're not _inherently_ hard to program. SDN is common, and definitely a scenario where FPGAs outperform GPUs. Same for machine learning. (FWIW, Google uses ASICs for both of these use cases.) What we need is a high level language and access to FPGAs. I've been interested in business opportunities in this area, but it's hard to monetize. What's somewhat surprising is that the language bit hasn't been solved in the open source world either. My suspicion is that the reason an open source language like Flow Tables doesn't exist (AFAIK) is that there's not widespread access to FPGAs.