the article is pretty weak, people have built rdma machines that size before, and there have been architectures that allow for direct memory addressability of t

the article is pretty weak, people have built rdma machines that size before, and there have been architectures that allow for direct memory addressability of that size before. so i have to assume the latter. that seems to be borne out by the little information i can find...addressable persistent memory is clearly a theme. but i haven't found any discussion of what kind of latency hiding mechanisms might be at play and what kind of consistency model is being used. will keep looking for anything detailed an authoritative (edit - this seems to be pretty relevant https://www.labs.hpe.com/publications...but https://www.labs.hpe.com/publications...but i don't know how much of it was speculative and how much was built...after all the security papers, there are some about concurrency control)