3 ms·

I'm not too sure about the "academic bias" point, since modern "CISC" CPUs are essentially "CISC on RISC" and essentially RISC already. That being said, greate

I'm not too sure about the "academic bias" point, since modern "CISC" CPUs are essentially "CISC on RISC" and essentially RISC already. That being said, greater efficiency is the main point, it's not too difficult to get a RISC-V core that beats (albeit marginally) an equivalent ARM core. Optimizing compilers can often be difficult though, especially if you want to use novel modifications to the backend to make things more efficient.

CalChris 9y ago
No, Skylake is not a RISC internally. Find something from the Intel Optimization Manual or their patents saying that. I been over this already. μops are hundreds of bits wide. Ain't nothing reduced about that. Read up on horizontal microprogramming. A RISC ISA is an encoding with an opcode. A μop is really just a long set of fields with some bits clocking some FUs on and others off. There is no decoding; there is no opcode.
- deepnotderp 9y ago
  I'm aware of horizontal microprogramming,and I checked again but I still don't see your point. Maybe link a reference?
  - CalChris 9y ago
    Smotherman. A complete macroinstruction is executed by generating an appropriately timed sequence of groups of control signals (micro-operations). http://www.frsn.utn.edu.ar/tecnicas3/manuales/Microprogramming_hist.pdf http://www.frsn.utn.edu.ar/tecnicas3/manuales/Microprogrammi... Originally, RISC cpus were hardwired but they are general purpose ISAs. RISC-V is fixed 32b ISA but has multiple formats controlled by an opcode. https://image.slidesharecdn.com/20160130deckyfosdemportinghelenostorisc-v-160130115431/95/porting-helenos-to-riscv-20-638.jpg https://image.slidesharecdn.com/20160130deckyfosdemportinghe... Original microprogrammed CPUs had a writeable control store (WCS). Modern processors translate CISC instructions into μops and cache this translation. The difference is the μop cache (μstore) vs WCS. FWIW, Skylake also has a WCS for obscure instructions. Microinstructions, μops, do not have an opcode. They are not decoded. Bits in a horizontal μop gate logic on/off directly. The RISC-V people do say RISC-like. https://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-130.html https://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-... And even that's wrong. But then they never even define what a RISC is. So RISC-like could be anything.

CalChris 9y ago

No, Skylake is not a RISC internally. Find something from the Intel Optimization Manual or their patents saying that. I been over this already. μops are hundreds of bits wide. Ain't nothing reduced about that. Read up on horizontal microprogramming. A RISC ISA is an encoding with an opcode. A μop is really just a long set of fields with some bits clocking some FUs on and others off. There is no decoding; there is no opcode.

deepnotderp 9y ago
I'm aware of horizontal microprogramming,and I checked again but I still don't see your point. Maybe link a reference?
- CalChris 9y ago
  Smotherman. A complete macroinstruction is executed by generating an appropriately timed sequence of groups of control signals (micro-operations). http://www.frsn.utn.edu.ar/tecnicas3/manuales/Microprogramming_hist.pdf http://www.frsn.utn.edu.ar/tecnicas3/manuales/Microprogrammi... Originally, RISC cpus were hardwired but they are general purpose ISAs. RISC-V is fixed 32b ISA but has multiple formats controlled by an opcode. https://image.slidesharecdn.com/20160130deckyfosdemportinghelenostorisc-v-160130115431/95/porting-helenos-to-riscv-20-638.jpg https://image.slidesharecdn.com/20160130deckyfosdemportinghe... Original microprogrammed CPUs had a writeable control store (WCS). Modern processors translate CISC instructions into μops and cache this translation. The difference is the μop cache (μstore) vs WCS. FWIW, Skylake also has a WCS for obscure instructions. Microinstructions, μops, do not have an opcode. They are not decoded. Bits in a horizontal μop gate logic on/off directly. The RISC-V people do say RISC-like. https://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-130.html https://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-... And even that's wrong. But then they never even define what a RISC is. So RISC-like could be anything.