4 ms·
> The main improvement we have made with the Neo architecture is we have hard (exact cycle count) guarantees on all memory movements on and off the chip ... Th
by kijiki 9y ago
> The main improvement we have made with the Neo architecture is we have hard (exact cycle count) guarantees on all memory movements on and off the chip ...
This is a fascinating idea, but I have a question.
What happens when the next process generation lets you improve cache timings? What about newer, faster DRAM (or whatever) timings?
Do I have to recompile the world in that case, to see any improvement in performance?
- trsohmers 9y agoThe assumption by us is that you would be recompiling from at least the LLVM IR level for each different version of the chip. This isn't a real problem for the markets we care about, as they have the source code for all of their applications. In the case of not wanting to distribute your source code, I am interested in being able to distribute emcrypted LLVM IR as a pseudo-binary, similar to how silicon IP companies deliver encrypted verilog and vhdl for integration into other chips.
- kijiki 9y agoInteresting. The traditional problem in this space is that the source code is lost or otherwise not available. It is not clear that some encrypted source analog to encrypted verilog would be more available.