> I don't know if anything similar exists in actual hardware. GreenArrays GA144 has a few similarities. It's an array of tiny Forth-optimized cores, with some

> I don't know if anything similar exists in actual hardware. GreenArrays GA144 has a few similarities. It's an array of tiny Forth-optimized cores, with some of them having specialized (mostly I/O) hardware. Apart from a few cores that are hardwired to boot from I/O pins, most need to be initialized via a neighbor. I don't remember where I saw this, but I remember reading that a rite of passage in GA144 programming is to write a "crawler" that loads itself into all of the cores. > Nodes numbered in green have one or two GPIO pins. Those in blue have analog I/O. Those in orange have digital I/O with specialized purposes: 001 and 701 have high speed SERDES; 705 has four pins which may be used for an SPI bus; 217, 517 and 715 have a GPIO pin whose read line is connected to one or more analog nodes for sample synchronization; and nodes 007, 8, and 9 together control two 18-bit parallel buses and four GPIO pins that may be used to control external memory chips. These and the SPI bus are of course available for other uses if desired. All nodes are suspended after reset, prepared to execute instructions coming from any neighbor node via a comm port. Six of these are also waiting for incoming signals on their pin(s) which will be interpreted as boot frames. 001 and 701 SERDES will execute instructions received; 200 listens for high speed 1-wire protocol, 300 for 2-wire synch, 708 for RS232 framed async, and 705 can boot from an SPI flash memory device. [1] http://www.greenarraychips.com/home/documents/index.html#architecture http://www.greenarraychips.com/home/documents/index.html#arc...