5 ms·

Have had a lot of fun with TIS-100. It's a very weird architecture, but it does teach the fundamentals of low-level coding, like using a single working register

Have had a lot of fun with TIS-100. It's a very weird architecture, but it does teach the fundamentals of low-level coding, like using a single working register, manipulating data in a simple way and using goto statements and branches for loops. A lot of the problems are problems due to the architecture though, not necessarily hard to implement in more conventional architectures. The article quickly goes over it, but for those who still wanna know more about the architecture, the TIS-100 is composed of nodes that can store a small number of lines of instruction code, have a working register, and have 4 I/O ports, UP, DOWN, LEFT and RIGHT. If asking for input, they will block until input is received from the specified adjacent node, and if passing output, they will block until the specified adjacent node asks for input. There are also memory nodes, introduced later in the game, to store more data. These nodes are on a grid. Some of them are disabled, and the memory nodes' placement differs from program/puzzle to program/puzzle. Thus, careful selection of nodes and I/O ports is required for completion. I don't know if anything similar exists in actual hardware. There's also a built-in "debugger" which simply allows you to run the program step by step and view all values, blocked nodes, and current instructions, which really helps, and possibly teaches players how to generally debug actual machine code. The programs run on a set of unit tests, and you can see which ones fail and why. In classic Zachtronics fashion, there's graphs explaining your performance in the end, in terms of time, and space. Users not familiar with actual hardware architecture principles won't probably be able to figure out themselves how to get the best time, because most problems require use of pipeline-like instructions, due to the blocking nature of the nodes. So while it teaches tricks and fundamentals, I don't think it teaches more advanced and important stuff. And that's not a bad thing, it's a great game. Would recommend to anyone.

0xcde4c3db 9y ago
> I don't know if anything similar exists in actual hardware. GreenArrays GA144 has a few similarities. It's an array of tiny Forth-optimized cores, with some of them having specialized (mostly I/O) hardware. Apart from a few cores that are hardwired to boot from I/O pins, most need to be initialized via a neighbor. I don't remember where I saw this, but I remember reading that a rite of passage in GA144 programming is to write a "crawler" that loads itself into all of the cores. > Nodes numbered in green have one or two GPIO pins. Those in blue have analog I/O. Those in orange have digital I/O with specialized purposes: 001 and 701 have high speed SERDES; 705 has four pins which may be used for an SPI bus; 217, 517 and 715 have a GPIO pin whose read line is connected to one or more analog nodes for sample synchronization; and nodes 007, 8, and 9 together control two 18-bit parallel buses and four GPIO pins that may be used to control external memory chips. These and the SPI bus are of course available for other uses if desired. All nodes are suspended after reset, prepared to execute instructions coming from any neighbor node via a comm port. Six of these are also waiting for incoming signals on their pin(s) which will be interpreted as boot frames. 001 and 701 SERDES will execute instructions received; 200 listens for high speed 1-wire protocol, 300 for 2-wire synch, 708 for RS232 framed async, and 705 can boot from an SPI flash memory device. [1] http://www.greenarraychips.com/home/documents/index.html#architecture http://www.greenarraychips.com/home/documents/index.html#arc...
- zokier 9y ago
  GA144 gets mentioned occasionally, but has anyone actually played with those chips? Apparently they are available in a hobbyist-friendly form bundled with a break-out board, which is nice. It might be neat idea to try to build a homebrew computer around the chip. Has GreenArrays scored any major sales (publicly), do we know if they have any future? It would be bit shame to see them go under.
pkaye 9y ago
> I don't know if anything similar exists in actual hardware. Closest thing in actual hardware is a systolic array architecture. Green Array, Parallela and Google's new machine learning processors are examples.
mcphage 9y ago
> A lot of the problems are problems due to the architecture though, not necessarily hard to implement in more conventional architectures. I think the biggest difficulty is due to the tiny # of instructions allowed per node. It's like 10, right?
- hcs 9y ago
  Yeah, in both TIS-100 and Shenzhen I/O the limits on number of instructions on a processor is probably the main thing keeping it from getting boring with straightforward implementations. Which works very well for me as a player!
  - LanceH 9y ago
    It also gets interesting when you start optimizing for time as you can get some parallel processing going and it's just a matter of syncing them for the output. Or if you optimize for number of cells use, you need to figure out how to do multiple things in 10 instructions.
em3rgent0rdr 9y ago
> I don't know if anything similar exists in actual hardware. Actually, there is a whole class of parallel architectures called "Systolic Arrays" which TIS and Shenzhen I/O belong to: https://en.m.wikipedia.org/wiki/Systolic_array https://en.m.wikipedia.org/wiki/Systolic_array
- convolvatron 9y ago
  but kungs iwarp machine was 32 bits wide, had a scratch sram (i forgot how big), and 32 registers it was a lot like programming a 32 bit arm, except there was a mov-to-my-neighbors file instruction .. and maybe full/empty bits?
  - em3rgent0rdr 9y ago
    iWarp is just one of the more recent systolic arrays. But they go back to atleast 1943 with the https://en.wikipedia.org/wiki/Colossus_computer https://en.wikipedia.org/wiki/Colossus_computer, and there is a lot of variety and topologies...but they all work by piping data around between modules.

0xcde4c3db 9y ago

> I don't know if anything similar exists in actual hardware. GreenArrays GA144 has a few similarities. It's an array of tiny Forth-optimized cores, with some of them having specialized (mostly I/O) hardware. Apart from a few cores that are hardwired to boot from I/O pins, most need to be initialized via a neighbor. I don't remember where I saw this, but I remember reading that a rite of passage in GA144 programming is to write a "crawler" that loads itself into all of the cores. > Nodes numbered in green have one or two GPIO pins. Those in blue have analog I/O. Those in orange have digital I/O with specialized purposes: 001 and 701 have high speed SERDES; 705 has four pins which may be used for an SPI bus; 217, 517 and 715 have a GPIO pin whose read line is connected to one or more analog nodes for sample synchronization; and nodes 007, 8, and 9 together control two 18-bit parallel buses and four GPIO pins that may be used to control external memory chips. These and the SPI bus are of course available for other uses if desired. All nodes are suspended after reset, prepared to execute instructions coming from any neighbor node via a comm port. Six of these are also waiting for incoming signals on their pin(s) which will be interpreted as boot frames. 001 and 701 SERDES will execute instructions received; 200 listens for high speed 1-wire protocol, 300 for 2-wire synch, 708 for RS232 framed async, and 705 can boot from an SPI flash memory device. [1] http://www.greenarraychips.com/home/documents/index.html#architecture http://www.greenarraychips.com/home/documents/index.html#arc...

zokier 9y ago
GA144 gets mentioned occasionally, but has anyone actually played with those chips? Apparently they are available in a hobbyist-friendly form bundled with a break-out board, which is nice. It might be neat idea to try to build a homebrew computer around the chip. Has GreenArrays scored any major sales (publicly), do we know if they have any future? It would be bit shame to see them go under.

pkaye 9y ago

> I don't know if anything similar exists in actual hardware. Closest thing in actual hardware is a systolic array architecture. Green Array, Parallela and Google's new machine learning processors are examples.

mcphage 9y ago

> A lot of the problems are problems due to the architecture though, not necessarily hard to implement in more conventional architectures. I think the biggest difficulty is due to the tiny # of instructions allowed per node. It's like 10, right?

hcs 9y ago
Yeah, in both TIS-100 and Shenzhen I/O the limits on number of instructions on a processor is probably the main thing keeping it from getting boring with straightforward implementations. Which works very well for me as a player!
- LanceH 9y ago
  It also gets interesting when you start optimizing for time as you can get some parallel processing going and it's just a matter of syncing them for the output. Or if you optimize for number of cells use, you need to figure out how to do multiple things in 10 instructions.

em3rgent0rdr 9y ago

> I don't know if anything similar exists in actual hardware. Actually, there is a whole class of parallel architectures called "Systolic Arrays" which TIS and Shenzhen I/O belong to: https://en.m.wikipedia.org/wiki/Systolic_array https://en.m.wikipedia.org/wiki/Systolic_array

convolvatron 9y ago
but kungs iwarp machine was 32 bits wide, had a scratch sram (i forgot how big), and 32 registers it was a lot like programming a 32 bit arm, except there was a mov-to-my-neighbors file instruction .. and maybe full/empty bits?
- em3rgent0rdr 9y ago
  iWarp is just one of the more recent systolic arrays. But they go back to atleast 1943 with the https://en.wikipedia.org/wiki/Colossus_computer https://en.wikipedia.org/wiki/Colossus_computer, and there is a lot of variety and topologies...but they all work by piping data around between modules.