To fully appreciate this, one would need much experience with microprocessor implementation. It's not reduced for the point of being simpler or smaller, but be

To fully appreciate this, one would need much experience with microprocessor implementation. It's not reduced for the point of being simpler or smaller, but because it represent a local optimum of perf/area for running C code, especially for small to medium implementations. However, much like the Alpha, RISC-V has been carefully designed to be efficient to scale UP, that is, to superscalar out-of-order implementations. Do read the spec and the footnotes; they are delightful: https://raw.githubusercontent.com/riscv/riscv-isa-manual/master/release/riscv-spec-v2.2.pdf https://raw.githubusercontent.com/riscv/riscv-isa-manual/mas...