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In that comment you say "RISC-V is thrown around like if it's an already working CPU but it is not" which is false since there are multiple existing, functionin
by jbarham 9y ago
In that comment you say "RISC-V is thrown around like if it's an already working CPU but it is not" which is false since there are multiple existing, functioning RISC-V implementations in silicon (https://www.sifive.com/products/freedom/ https://www.sifive.com/products/freedom/), FPGAs and software (https://bellard.org/riscvemu/ https://bellard.org/riscvemu/).
Most people on HN should understand the difference between an ISA specification and its implementation in silicon.
- sweden 9y agoThe tone of your comment is very unfortunate taking into account the content of it. The second like you showed is just a simple FPGA implementation, you can't really use for ASIC designs. The first one is a completely different implementation by a different company. And they are not really providing the whole source. I challenge you to find a place to download their designs yourself. I will be waiting.
- FullyFunctional 9y agoThe second is real silicon. I have a couple. But all this talk is missing the point. For companies looking to design a product for which the processors is a means to an end, RISC-V holds a tremendous time-to-market advantage and full complete control of your own destiny. That, more than anything, will matter for the 1st wave of adopters. (RV has other technical merits that you for some reason discount).