Here's a minimal Forth implementation built in Verilog to run on a Lattice iCE40 FPGA: https://github.com/jamesbowman/swapforth/tree/master/j1a https://github.

Here's a minimal Forth implementation built in Verilog to run on a Lattice iCE40 FPGA: https://github.com/jamesbowman/swapforth/tree/master/j1a https://github.com/jamesbowman/swapforth/tree/master/j1a