I sort of consider x86 ISAs barely CISCy - almost all x86 instructions that access memory involve a single address (so one TLB dip even if you're doing RMW) - t

I sort of consider x86 ISAs barely CISCy - almost all x86 instructions that access memory involve a single address (so one TLB dip even if you're doing RMW) - this makes it easy to decompose instructions into uOPs. IMHO 'Real' CISCs potentially have multiple memory addresses "add m1, m2, m3" sort of things and addressing modes that do double indirections (remember a worst case VAX instruction could generate [I think] 27 different TLB misses which meant that the smallest process had to have an at least 27 page minimum working set to let every program progress - for a RISC machine it's just 2) Really though what happened between RISC/CISC was largely driven by a change in the relative speeds of memory and CPUs - CISCs made sense when memory bandwidth was low and heavy encoding reduced instruction bandwidth, RISCs (or RISCish including x86s) have come to dominate as caches moved on-chip and bandwidth soared