4 ms·

Cool project! I see lots of toy RISC CPUs but rarely anything CISCy. This sort of thing is great as a house-keeping core for bigger RTL designs, especially as i

by bem94 9y ago

Cool project! I see lots of toy RISC CPUs but rarely anything CISCy. This sort of thing is great as a house-keeping core for bigger RTL designs, especially as it is synthesis-able. Are you planning to extend the ISA at all?

jacquesm 9y ago
I'm not sure if < 40 instructions should count as 'CISC' by any definition. Besides the instructions that are implemented fall squarely in the 'RISC' domain: low count, very few addressing modes, memory access separate from operations.
- microtherion 9y ago
  "Move immediate value to memory address" seems like a prototypically CISCy operation to me.
  - ajb 9y ago
    Typical CISC is an instructions which uses both a load/store pipeline slot and an ALU pipeline slot. 'move immediate to address' just uses a load/store slot and fits into a normal risc microarchitecture; the reason you don't normally get it is encoding constraints: the address typically uses the instruction bits where the immediate would go. Looking at the source, though, this processor uses a variable length instruction; so it is at least a bit CISCy.
- Taniwha 9y ago
  I sort of consider x86 ISAs barely CISCy - almost all x86 instructions that access memory involve a single address (so one TLB dip even if you're doing RMW) - this makes it easy to decompose instructions into uOPs. IMHO 'Real' CISCs potentially have multiple memory addresses "add m1, m2, m3" sort of things and addressing modes that do double indirections (remember a worst case VAX instruction could generate [I think] 27 different TLB misses which meant that the smallest process had to have an at least 27 page minimum working set to let every program progress - for a RISC machine it's just 2) Really though what happened between RISC/CISC was largely driven by a change in the relative speeds of memory and CPUs - CISCs made sense when memory bandwidth was low and heavy encoding reduced instruction bandwidth, RISCs (or RISCish including x86s) have come to dominate as caches moved on-chip and bandwidth soared
ruchira66 9y ago
Adding new instruction to this processor is pretty easy! But I'm little bit busy right now. I'll do it whenever I get free time!

by bem94 9y ago

jacquesm 9y ago

I'm not sure if < 40 instructions should count as 'CISC' by any definition. Besides the instructions that are implemented fall squarely in the 'RISC' domain: low count, very few addressing modes, memory access separate from operations.

microtherion 9y ago
"Move immediate value to memory address" seems like a prototypically CISCy operation to me.
- ajb 9y ago
  Typical CISC is an instructions which uses both a load/store pipeline slot and an ALU pipeline slot. 'move immediate to address' just uses a load/store slot and fits into a normal risc microarchitecture; the reason you don't normally get it is encoding constraints: the address typically uses the instruction bits where the immediate would go. Looking at the source, though, this processor uses a variable length instruction; so it is at least a bit CISCy.
Taniwha 9y ago
I sort of consider x86 ISAs barely CISCy - almost all x86 instructions that access memory involve a single address (so one TLB dip even if you're doing RMW) - this makes it easy to decompose instructions into uOPs. IMHO 'Real' CISCs potentially have multiple memory addresses "add m1, m2, m3" sort of things and addressing modes that do double indirections (remember a worst case VAX instruction could generate [I think] 27 different TLB misses which meant that the smallest process had to have an at least 27 page minimum working set to let every program progress - for a RISC machine it's just 2) Really though what happened between RISC/CISC was largely driven by a change in the relative speeds of memory and CPUs - CISCs made sense when memory bandwidth was low and heavy encoding reduced instruction bandwidth, RISCs (or RISCish including x86s) have come to dominate as caches moved on-chip and bandwidth soared

ruchira66 9y ago

Adding new instruction to this processor is pretty easy! But I'm little bit busy right now. I'll do it whenever I get free time!