Having used both for multiple years, I prefer Verilog. I think that for the synthesized subset of RTL, that HDL is typically used for, Verilog is way more produ

Having used both for multiple years, I prefer Verilog. I think that for the synthesized subset of RTL, that HDL is typically used for, Verilog is way more productive than VHDL. The endless type conversions that are required for VHDL, just means too much mental burden and is away from actual design effort. VHDL is not practical. Strong typing is useful when you use the same types for multiple instances, as in SW. However in HW, you construct your data to a set of bits, and then take as many as needed for the particular case. The type you need is a bit vector. Bit slicing checks can be done in the Linter tool, if needed. In DSP designs you can get benefits from VHDL types for signed and unsigned integers, but in my opinion even that does not cover the VHDL related deficiencies. When you are working with synthesizable subset, you will never have problems with race conditions in simulation. You stick to a strict coding style, and it becomes the second nature. For beginners there are always issues, including this. I find comparing the merits of SW languages to HW languages a bit silly. Describing SW does not benefit from the same features that describing HW does. For example Functional Programming (aka Haskell people) has nothing to do with HW. In FP you want to separate state from your functions. In HW the intention is to do the exact opposite. You want capture everything as local as possible, in order to enable maximum performance in speed, power, and area. This implies that OOP is pretty close to what HW requires, but not FP.