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As a Haskell fan I was drawn toward VHDL because of its "strong typing". Haha, it's nothing like what I expected, mainly just a bunch of annoying forced casts
by daxfohl 10y ago
As a Haskell fan I was drawn toward VHDL because of its "strong typing". Haha, it's nothing like what I expected, mainly just a bunch of annoying forced casts from signed to unsigned etc. I ended up liking Verilog better: more characters are dedicated to your intent than to your casts. But ultimately they're not that different.
(Note there are also Haskell-oriented HDL's, but my experience with those wasn't great, at least 4-5 years ago. Proprietary, poor interop, and let's face it, it's not Haskell. On the surface FP seems like a good fit for FPGA, but in the trenches you constantly need lower-level tricks to keep your program's gate count from exploding.)
- oelang 10y agoLet me guess, you were downcasting everything to std_logic_vector? If you have to cast things all the time in VHDL you're not using it correctly. But please enjoy (System)Verilog with it's random often undefined coercion, implicit wire declarations, non-deterministic simulation and lack of any meaningful compile-time checks. Honestly, as a huge Haskell fan, I can't believe you're a Haskell fan.
- daxfohl 10y agoGeesh, does reporting my experience with the two languages really warrant this kind of snarky ad-hominem attack?