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At a recent Intel event I spoke to a senior Altera engineer and he recommended just using OpenCL and not bothering with either VHDL or Verilog. Apparently the O
by rsp1984 9y ago
At a recent Intel event I spoke to a senior Altera engineer and he recommended just using OpenCL and not bothering with either VHDL or Verilog. Apparently the OpenCL to FPGA compilers these days have become so good that the performance is within 10%-30% of hand-written VHDL / Verilog, which for most use-cases is very much in the "good enough" range.
- oelang 9y agoNo they haven't and they are not even close. OpenCL is a bad language for synthesis. The strength of an FPGA is deeply-pipeline-able sequential algorithms. C-based languages just aren't good at expressing/controlling pipelining, so the synthesizer/compiler has to infer this but that problem is too hard. You could change 1 line of code, a minor fixup and the clever optimizer fails and your design is suddenly 10x as big.
- kingosticks 9y agoIf you're happy to throw away up to 30% of your performance I think you've got to question why you're designing hardware, even on FPGAs. It probably is good news for Altera as you'll now need a higher spec device to solve your problem.