3 ms·
I'd say go with Verilog. SystemVerilog 2013 and VHDL 2008 are competitive when it comes to synthesis features, but synthesis is only half of the story. SV's si
by nrclark 9y ago
I'd say go with Verilog. SystemVerilog 2013 and VHDL 2008 are competitive when it comes to synthesis features, but synthesis is only half of the story.
SV's simulation features are really top-notch. If you're going to pick one to learn, I'd go with SV because you'll probably be using it anyways for verification tasks.