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> Neural nets are honestly best suited to a ZISC type architecture... In any case, specialized deep learning chips should be on their way. Google's TPU archite
by wolfgke 10y ago
> Neural nets are honestly best suited to a ZISC type architecture... In any case, specialized deep learning chips should be on their way.
Google's TPU architecture is CISC type instead of ZISC type: https://www.nextplatform.com/2017/04/05/first-depth-look-googles-tpu-architecture/ https://www.nextplatform.com/2017/04/05/first-depth-look-goo...
- dom0 10y agoI don't really agree. What is labelled a "CISC instruction set" here would more usually just be called a control interface. But maybe I'm missing some sort of context here. (Contrasting it with "ZISC" for marketing purposes?)
- wolfgke 10y ago> Contrasting it with "ZISC" for marketing purposes? I don't understand what you want to say: ZISC is a rather different concept: https://en.wikipedia.org/wiki/Zero_instruction_set_computer https://en.wikipedia.org/wiki/Zero_instruction_set_computer
- deepnotderp 10y agoI don't actually think that the Google TPU is the paragon of deep learning processor architecture, there are a lot of things that I don't think are done very well. In any case, that being said, the TPU is less of a CISC and much more like a lightweight RISC control mechanism.