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Because your course is based on outdated materials. In the 80s and 90s academia and high-end computing was taken by a RISC illusion. RISC architectures were si
by dom0 10y ago
Because your course is based on outdated materials.
In the 80s and 90s academia and high-end computing was taken by a RISC illusion. RISC architectures were simple and clean and easy to implement at higher performance than any CISC processor of the time, so people assumed that of course RISC would be the feature, right? Well, no. CISC, or, to be more truthful, x86 was a mass-market item with competing manufacturers with deep pockets (like Intel and AMD).
In the mid 90s both Intel and AMD broke RISCs neck (though it was not immediately clear perhaps what a groundbreaking innovation this was): They introduced processors that translated x86 instructions to other instructions (µops) that were then scheduled and executed. Turns out, this is pretty efficient for a number of reasons (1- you get existing software 2- x86 code can be really dense; RISC had instruction bloat issues 3- decoding insns is only a very small part of what a CPU does and does only consume a minority in transistors 4- you can change the µops, they are an implementation detail, to best suit the exact core at hand; something impossible for RISC). This allowed x86 all benefits of what RISC previously had for itself.
By ~2000 most RISC architectures were dead (Alpha, SGI, ...) with only POWER and SPARC surviving in their niche markets.
In summary: The importance of the ISA was vastly overestimated by researchers, who assumed that this was a blocking issue to make x86 go faster. In the end, x86 won, because x86 had the bigger market with more money in it.
- pcwalton 10y ago> By ~2000 most RISC architectures were dead (Alpha, SGI, ...) with only POWER and SPARC surviving in their niche markets. You forgot ARM, which is a major omission. > In the end, x86 won, because x86 had the bigger market with more money in it. It's not the end yet. :) x86's dominance in the future is hardly assured, and in fact if you measure by total number of microprocessors sold, x86 is a small niche--300-400 million sales per year compared to 15 billion ARM chips sold.
- dom0 10y agoThis thread is about high performance. I.e. desktop, workstation, server processors. > Why are x86/64 processors used for most high performance applications then? Also ARM, the architecture where most cores have between three and four distinct frontends, hardly qualifies as R ISC.
- pcwalton 10y agoEven with the complexity of Thumb-1, Thumb-2, and NEON, I'd give the edge to ARM in simplicity. At least the instruction encodings for ARM make sense, even today. x86 instruction decoding is absurd. More importantly, ARM has a way to massively reduce its decoding complexity, via AArch64. AArch64 is a separate RISC instruction set, with room explicitly left in the design for dropping 32-bit ARM in the future (32-bit support is optional, though in practice today everyone includes it). ARM is effectively in the process of making a transition to a more RISC-like ISA, unlike Intel which has no realistic way to get there.
- wolfgke 10y ago> Even with the complexity of Thumb-1, Thumb-2, and NEON, I'd give the edge to ARM in simplicity. At least the instruction encodings for ARM make sense, even today. x86 instruction decoding is absurd. If you write down the x86 instruction encoding in octal, it makes a lot more sense: > http://www.dabo.de/ccc99/www.camp.ccc.de/radio/help.txt http://www.dabo.de/ccc99/www.camp.ccc.de/radio/help.txt
- pcwalton 10y agoFor the 8086, sure. But modern x86 throws in Mod R/M, SIB bytes, REX prefixes, VEX prefixes, Operand Size Overrides…
- dom0 10y agoSo? Samsung also sells a lot more smartphones than Apple, yet Apple makes far more profit from them. You can't pay R&D with revenue. There are probably more PowerPC chips sold via laser printers and such than x86 chips. Conversely, 8051 derivates probably outnumber all of these. So what. Meaningless argument.
- pcwalton 10y agoIt's pretty hard to make an argument in 2017 that Intel is in a better economic position than its mobile competitors by focusing on the PC market.
- jcranmer 10y agoARM instructions let you do r1 = r2 + (r3 << r4) if CC, and that's just basic instruction set. That's as much an affront to RISC as x86 is.
- pcwalton 10y agoNot in AArch64 IIRC.
- Questron 10y agoOnly the condition code was removed. Otherwise the parent is right and there really is an enormous amount of instructions. Fortunately less than intel, but still a lot.
- pcwalton 10y agoI don't think you can do variable length shift with an arithmetic instruction in AArch64 either: only immediate shifts.
- smitherfield 10y agoThat's not accessing memory, so there's no reason it couldn't be (reasonably) efficiently pipelined without decoding to µops.
- thetinguy 10y ago-deleted-
- detaro 10y agoThe parent comment mentions this already.