2 ms·
See: RISC-V not having a negate instruction, because it's encoded as SUB 0, $X. Similarly no bitwise-not because XOR -1, $X
by __s 10y ago
See: RISC-V not having a negate instruction, because it's encoded as SUB 0, $X. Similarly no bitwise-not because XOR -1, $X
- baobrien 10y agoAlso no explicit register move instruction, it's ADDI rd,rs1,0. NOP is ADDI x0,x0,0.