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Neural nets are honestly best suited to a ZISC type architecture... In any case, specialized deep learning chips should be on their way. Not to toot my own hor
by deepnotderp 10y ago
Neural nets are honestly best suited to a ZISC type architecture... In any case, specialized deep learning chips should be on their way.
Not to toot my own horn here, but we're one of the hopeful deep learning chip startups, I'd be happy to answer any more questions or perhaps elaborate on why I think ZISC is better for neural nets.
- dom0 10y agoIt's almost always better to have a dedicated chip implement some algorithm, if it makes economic sense to do so. From hard drive controllers to Google's TPU.
- deepnotderp 10y agoDeep learning processor != an ASIC If you burned an ASIC for a single type of network architecture, then that would be something else.
- CalChris 10y agoThe TPU is an ASIC. The result is called a Tensor Processing Unit (TPU), a custom ASIC we built specifically for machine learning. https://cloudplatform.googleblog.com/2016/05/Google-supercharges-machine-learning-tasks-with-custom-chip.html https://cloudplatform.googleblog.com/2016/05/Google-supercha...
- deepnotderp 10y agoPerhaps it's a confusion of terminology, because most people I know would call it as asip. It has the flexibility to implement any linear operation after all.
- wolfgke 10y ago> Neural nets are honestly best suited to a ZISC type architecture... In any case, specialized deep learning chips should be on their way. Google's TPU architecture is CISC type instead of ZISC type: https://www.nextplatform.com/2017/04/05/first-depth-look-googles-tpu-architecture/ https://www.nextplatform.com/2017/04/05/first-depth-look-goo...
- dom0 10y agoI don't really agree. What is labelled a "CISC instruction set" here would more usually just be called a control interface. But maybe I'm missing some sort of context here. (Contrasting it with "ZISC" for marketing purposes?)
- wolfgke 10y ago> Contrasting it with "ZISC" for marketing purposes? I don't understand what you want to say: ZISC is a rather different concept: https://en.wikipedia.org/wiki/Zero_instruction_set_computer https://en.wikipedia.org/wiki/Zero_instruction_set_computer
- deepnotderp 10y agoI don't actually think that the Google TPU is the paragon of deep learning processor architecture, there are a lot of things that I don't think are done very well. In any case, that being said, the TPU is less of a CISC and much more like a lightweight RISC control mechanism.
- odbol 10y agoIs there any systems out there that would let me program on a ZISC, today?