4 ms·
I'm not sure I would say more complicated, but you're completely right things are bit different on the byte level. For example there are certain prefixes that c
by DSMan195276 10y ago
I'm not sure I would say more complicated, but you're completely right things are bit different on the byte level. For example there are certain prefixes that can be added indefinitely. Because of that there is a maximum instruction length x86 CPUs will decode, which I believe is 15 bytes - no valid instructions will go over that without adding unneeded prefixes, but without such a maximum the instruction set is technically infinite in length.
That said, as far as the CPU is concerned (And keep in mind, x86 CPUs are stupid complicated so none of what I'm about to describe would really tell you how a particular x86 executes a particular instruction. This would apply better to simpler CPUs) an instruction with multiple widths is generally treated the same way for all of the widths. It decodes the opcode identifier for the instruction, and then would go on the decode the width from a separate part of the instruction. (Though I mean, commonly simple CPUs don't even support multiple widths). The hardware that handles that would commonly be the same or very similar. Debating whether or not that makes them "different" is just matter of definitions I think. But at the end of the day they are generally treated very similarly.
It's also worth noting that assembly langauge's aren't quite a one-to-one mapping. It's fairly common for the assembler to substitute an equivalent instruction for one you used in cases where it knows it is better, and it is also common that a instruction doesn't actually exist on the CPU, but the mnemonics for it exists for convenience. But this does mean that the assembly language can actually represent more instructions then the CPU actually has, meaning the 'byte level' version can in some ways be less complicated, depending on your POV. I think for x86 this likely doesn't really make much of a difference though because the number probably isn't extremely high.
- __s 10y agoSee: RISC-V not having a negate instruction, because it's encoded as SUB 0, $X. Similarly no bitwise-not because XOR -1, $X
- baobrien 10y agoAlso no explicit register move instruction, it's ADDI rd,rs1,0. NOP is ADDI x0,x0,0.
- throwaway91111 10y agoI believe the longest valid instruction is 17 bytes, but it's been years since I knew how to construct it.