3 ms·
I was doing some back of the envelope math for a blog post last night[1] and it looks like we're not that far away from the limits of what's possible - at least
by Symmetry 10y ago
I was doing some back of the envelope math for a blog post last night[1] and it looks like we're not that far away from the limits of what's possible - at least for non-reversible computing. Getting rid of a bit of information as in a Nand get is always going to cost at least 2.75 zeptoJoules and current transistor technology can do it for an attoJoule, so just another factor of 360 to go. Of course then we can try to transition to reversible computing to get around that[2].
[1]http://hopefullyintersting.blogspot.com/2017/04/the-coming-interregnum-after-moores-law.html http://hopefullyintersting.blogspot.com/2017/04/the-coming-i...
[2]https://en.wikipedia.org/wiki/Reversible_computing https://en.wikipedia.org/wiki/Reversible_computing
- rocqua 10y agoIf I recall correctly, the lower bound on energy for destroying a bit depends (linearly?) on the temperature. Couldn't performance then be improved by cooling?
- Symmetry 10y agoYes, you're correct and I probably should have mentioned that.
- jacquesm 10y agoI don't think it will matter much though. Whether you have to remove input power as heat or expend power to cool likely won't make a whole lot of difference. Just that the delta-t will be a lot larger and so it may actually cost more to keep that ultra-cool machine ultra-cool. Maybe future data-centers will be used to pre-heat the water that goes into the turbines that power the electricity plant, in some kind of perverse version of a perpetuum mobile. You'd need to make up for the difference lost on each cycle with extra fuel.
- monort 10y agoWhere did you get the number for attojoule per gate operation?
- wtallis 10y agoA factor of 360 is closer than I would have guessed. But that's still at least 8 doublings of compute efficiency. We've never had concrete roadmaps that far out—that would be like scheduling the introduction of FinFETs while Pentium 2s were first hitting the shelves. Nobody's ever been able to predict that far in advance which fabrication technologies will end up being economical at scale and required at which node. (Just look at how well the industry has coped with having to put off EUV so many times.) With the looming end of silicon scaling, those thermodynamic limits certainly don't look any less out of reach.