3 ms·
That the smart branches optimization requires a workaround in the IR codegen concerns me a bit. It makes sense in a HW context, like MIPS branch delay slots, bu
by Vogtinator 10y ago
That the smart branches optimization requires a workaround in the IR codegen concerns me a bit. It makes sense in a HW context, like MIPS branch delay slots, but not really here. There could be a flag in the branch instruction that disables the optimization at least.