The other issue that people miss here is the physical board that the switch ASIC is on. People might want to google SerDes and XAUI. The simplified bit here is

The other issue that people miss here is the physical board that the switch ASIC is on. People might want to google SerDes and XAUI. The simplified bit here is back in the day first 10G you had 4 x 3.25G lanes. So for example for the Fulcrum FM4000 (24x10G) you had 64 traces on the board, 4 to each port. For something like the Broadcom Trident+ which could do 64 ports of 10G you have 256 traces. For each 10G there are 4 and they have to line up to the nm on the board unless you wanted to use a PHY and / or retimers. Arista shipped the 1st PHYless design of this. Less parts, higher MTBF, less heat and also less latency (phy add latency). To do 40G you would need 16 of the 3.25 (yuk). Things moved to 4x10G lanes and you got 40G ports. With the 25G Ethernet the lanes moved to 4x25G so you get 100G ports. Anyway random stuff if anyone is interested. Yes I know I am mixing the Serdes and XAUI stuff but this is a simpler view just talking about the lanes from the chip. Google will give great answers if you want to dig deeper.