5 ms·
It seems like an systolic array architecture using Forth processors as the processing nodes. Good for some things like neural networks like Google is doing with
by pkaye 10y ago
It seems like an systolic array architecture using Forth processors as the processing nodes. Good for some things like neural networks like Google is doing with their own chips. There is also Parallela which was on Kickstarter. But I'm not sure if Moore is doing anything fundamentally new unless their compiler can automatically convert a conventional program into systolic array form?
- agumonkey 10y agoMoore is also quite old (80), I'm even worried about his passing from time to time. So I suppose he's not doing much ambitious things but enjoying himself. Parallela has managed to conduct a very succesful KickStarter. They've been under the radar since but still active, they published new plans for 1000 core coprocessor array. And I suppose, now they've proved themselves alone, they won't stop soon.
- jcbeard 10y agoYou might want to check out "A Systolic Array Optimizing Compiler" -> https://books.google.com/books?id=6nTjBwAAQBAJ&lpg=PA188&ots=6lBIbFrhBa&dq=a%20systolic%20array%20optimizing%20compiler&pg=PP4#v=onepage&q=a%20systolic%20array%20optimizing%20compiler&f=false https://books.google.com/books?id=6nTjBwAAQBAJ&lpg=PA188&ots... Systolic array/vector processors have been used since the late 60's for neural and other gemm heavy workloads. The Warp architecture from CMU is an excellent example.