The memory wall is not a bandwidth issue, but a problem of (concurrent - many more strands of execution than memory channels) latency and there are as far as I

The memory wall is not a bandwidth issue, but a problem of (concurrent - many more strands of execution than memory channels) latency and there are as far as I know pretty much no ideas how to fundamentally address that (DRAM alternatives might, but so far were all rather disappointing even compared to much older DRAM). You can add more channels and more ranks into the system, which gives some small linear increase w.r.t. to concurrency, but brings a a big (channels) or minor (ranks) power increase. This doesn't change non-concurrent latency, so does not help sequential workloads.