LLVM backend developers generally write in TableGen. Their assembly knowledge to say nothing of their microarchitectural knowledge is limited. That may sound h

LLVM backend developers generally write in TableGen. Their assembly knowledge to say nothing of their microarchitectural knowledge is limited. That may sound harsh but it's actually the point of a good compiler design (which LLVM has). You can write an optimizer pass without understanding the C parser. You can write a backend without understanding register allocation. You can get something working without really getting it tuned. You can specify superscalar machine instruction scheduling latencies without really understanding instruction scheduling itself. https://github.com/llvm-mirror/llvm/blob/master/lib/Target/AArch64/AArch64SchedCyclone.td https://github.com/llvm-mirror/llvm/blob/master/lib/Target/A...