3 ms·
You could probably have Page 0 be a user managed cache though - keep it in SRAM directly on the CPU die.
by slededit 10y ago
You could probably have Page 0 be a user managed cache though - keep it in SRAM directly on the CPU die.
- AstralStorm 10y agoTLB (page table) is already kept in the CPU, in SRAM. Memory controller is as well. If users can manage cache, they can write code that is efficient with current architecture as well. I'm not seeing this.