5 ms·
A commonly recurring subject on the 6502 forums is what a "modern" 6502 would look like. It always boils down to not really being able to replicate the 1-cycle
by white-flame 10y ago
A commonly recurring subject on the 6502 forums is what a "modern" 6502 would look like. It always boils down to not really being able to replicate the 1-cycle access to any byte in RAM. Changes to the memory access model requires changing everything to being unrecognizable as a 6502 derivative, in programming style.
Of course, you could put 64KB of SRAM on the CPU die, but the size and power of the RAM would dwarf the processor, and you'd get an old-school 6502, arguably not a modern take on the concept. If you want more memory, you simply can't replicate the 1980s access model at anything approaching today's speeds.
- PaulHoule 10y agoI was wondering the other day how it would work if you made something like a 6502 out of indium phosphide with 64k of SRAM and clocked it at 50 GHz.
- qb45 10y agoThis would have to be a tiny core with tiny RAM indeed. At 50GHz your clock signal is 180° out of phase after traveling just 2mm. I wonder if there are any practical applications that could benefit from such a thing.
- PaulHoule 10y agoCommunications and signal processing, maybe.
- white-flame 10y agoFully asynchronous designs that send a local activity pulse along with their data, perhaps.
- slededit 10y agoYou could probably have Page 0 be a user managed cache though - keep it in SRAM directly on the CPU die.
- AstralStorm 10y agoTLB (page table) is already kept in the CPU, in SRAM. Memory controller is as well. If users can manage cache, they can write code that is efficient with current architecture as well. I'm not seeing this.