> Changing the parameters means changing the ISA. That's not true. One just needs to _add_ to the ISA. That's exactly what SSE and AVX do: oodles of registers,

> Changing the parameters means changing the ISA. That's not true. One just needs to _add_ to the ISA. That's exactly what SSE and AVX do: oodles of registers, oodles of compute power. Apparently those are to be used by those specialized libraries you mention. OOO, register-renaming, and having the ability of hundreds of instruction in flight (!) seem more about improving general computing performance. > Practically no optimizations found in CPUs do that (looking at "run-time values"). Or I'm misreading you here. Modern CPUs are like essentially like trace optimizers that do depend on run-time values. For one, there's the branch predictor. Secondly, instructions may execute as soon as the dependent data becomes available. So it's possible that some memory load happens quickly because data is in L1, compared to another independent instruction doing a memory load from main memory. Since the data from one instruction arrived earlier, it can get scheduled ahead of the other -- in real time.