4 ms·
You will get the number of instructions in parallel that is the minimum of (a) the number of instructions that can be handled by the hardware simultaneously and
by gvb 10y ago
You will get the number of instructions in parallel that is the minimum of (a) the number of instructions that can be handled by the hardware simultaneously and (b) the number of instructions that don't have inter-dependencies.
My example was not a 3 instruction example. It was a minimum example of data dependencies. In the example, until the CPU can resolve what the value of the variable (register) "a" is, it cannot do the calculation for the variable "c". Most programs have a high level of data inter-dependencies. Conditional branches are major class of data inter-dependency - the CPU cannot execute code beyond the branch[1] until it knows which branch it will take.
There is a class of programs that are "embarrassingly parallel" that having more execution units will speed them up, ideally linearly (graphics GPUs are a classic example). "Garden variety" programs end up under utilizing execution units because the execution unit assigned to calculate "c" (from my example) will be stalled waiting for execution units assigned to calculate "a" and "b" to complete their calculations.
This is related to the long unrealized, and still unrealized, promise of VLIW architectures.
https://en.wikipedia.org/wiki/Very_long_instruction_word https://en.wikipedia.org/wiki/Very_long_instruction_word
[1] A small-ish lie: many processors nowadays do "speculative execution" where they guess which branch will be taken and execute ahead. If they guess right, they win. If they guess wrong, they throw away the work they did and restart the execution on the other branch.
- psykotic 10y agoEven with an embarrassingly parallel problem, you need to have enough compute work per memory access to achieve anything like full utilization. Suppose you're doing a pairwise multiplication of two huge arrays. That's as embarrassingly parallel as it gets. Even better, it's a perfect fit for SIMD. But as the article shows, you'll get nowhere near the theoretical throughput of 4 instructions/cycle since there's not enough main memory bandwidth. You could add infinitely large issue and retire queues and infinitely many execution units to the out-of-order core. You'd still be bottlenecked by memory bandwidth.