Memory controllers are not so simple to do, and fast MCs also eat quite a bit of power. So a simple reason that they didn't do it could be either a) they did n

Memory controllers are not so simple to do, and fast MCs also eat quite a bit of power. So a simple reason that they didn't do it could be either a) they did not want to license a more expensive, faster design b) while it would be faster, it would decrease efficiency to a point that did not meet their goals (for data centers, efficiency > absolute performance, within reasonable boundaries) c) like b) just with cost of memory d) GDDR5 and DDR3/4 have different design trade-offs. The former is optimized for sequential bandwidth (and low capacity; GDDR always was a point-to-point memory bus just to achieve the clock speeds), while DDR3/4 takes random read/write workloads into account (eh... to the amount possible with DRAM...) -- HBM requires a silicon interposer, which is basically like another complete chip (just without the FEOL parts, "just" metallization), that has to be significantly larger than the size of all chips combined. So unless you really need that performance or have a volume product it's unlikely to be a good deal.