3 ms·
Those limitations sounds awfully similar to that of an FPGA..
by pavanky 10y ago
Those limitations sounds awfully similar to that of an FPGA..
- vvanders 10y agoI was going to say as well. It seems like if caches are the bane of sequential processing(CPU) then routing has to be the counterpart on the parallel(FPGA/ASIC) side of the equation.