> May still be using a physical register for [r15], despite the slow-looking dereference I don't think so. I believe register renaming means two explicit uses

> May still be using a physical register for [r15], despite the slow-looking dereference I don't think so. I believe register renaming means two explicit uses of a register may not end up in the same physical register, it doesn't mean loads can be promoted into registers, as that would require maintaining cache coherency at a level even deeper inside to an individual core than just L1 cache. It is extremely likely that the load will hit L1 cache, but this isn't quite the same as being in a register.