I'm one of the core devs of MyHDL(https://github.com/myhdl/myhdl https://github.com/myhdl/myhdl). It does most of what you're describing and converts to both Ve

I'm one of the core devs of MyHDL(https://github.com/myhdl/myhdl https://github.com/myhdl/myhdl). It does most of what you're describing and converts to both Verilog and VHDL. I'll be happy to answer any questions you have.