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For anyone interested in developping applications for FPGAs in a high-level DSL embedded in Scala, this project (https://github.com/stanford-ppl/spatial-lang ht
by rubenfiszel 10y ago
For anyone interested in developping applications for FPGAs in a high-level DSL embedded in Scala, this project (https://github.com/stanford-ppl/spatial-lang https://github.com/stanford-ppl/spatial-lang) from a Stanford Lab might interest you.
Disclaimer: I am part of the lab.
- spamizbad 10y agoI noticed there's a lot of RISC-V cores today implemented in Berkeley's Chisel (https://chisel.eecs.berkeley.edu/ https://chisel.eecs.berkeley.edu/). How would you say they compare?
- rubenfiszel 10y agoActually, Chisel is one of our main target codegen. We aim to be more high-level than Chisel. See here for a quick and very incomplete tour: http://spatial-lang.readthedocs.io/en/latest/tutorial.html http://spatial-lang.readthedocs.io/en/latest/tutorial.html
- krapht 10y agoI was never able to convince my coworkers to program in FPGA HLLs, just because when you need to debug and simulate, you have to touch VHDL/Verilog in order to communicate with the board and understand what your high level abstraction is compiling to (not to mention the great deal of work that relies on tweaking and instantiating FPGA parameters like clock lines, buffers, DSP cells, etc). And actually this takes up the majority of the design time... so to make a software analogy, why bother writing in Scala when you have to verify and debug at at the assembly level?
- smaddox 10y agoIs that a serious question? Because most software development is now done in high level languages. With the proper abstractions, there's no need to debug the high level code at the assembly level; you just need to debug the abstractions.
- krapht 10y agoMaybe I should have made a different comparison: you can write a kernel driver in Python, but maybe you shouldn't. Debugging your HLS compiler is not a process full of joy and happiness.