No, it's a fundamental issue with the technology. Roughly, the ratio of power density to capacity-that-can-hold-information-for-a-refresh-interval stays more or

No, it's a fundamental issue with the technology. Roughly, the ratio of power density to capacity-that-can-hold-information-for-a-refresh-interval stays more or less constant, independent of fab node. In fact, newer generations (DDR3, DDR4) have been pushing it here (cf. rowhammer). I doubt we will see a drastic improvement in DRAM latency unless the underlying process changes a lot (i.e. different physical storage mechanism or very different manufacturing).