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I've heard that modern processors are designed with the expectation (or even a requirement) that no more than 10% of the chip will be active at once. In additio
by p1esk 10y ago
I've heard that modern processors are designed with the expectation (or even a requirement) that no more than 10% of the chip will be active at once. In addition, there are power density constraints (even those 10% of the chip that can be active at once must not be concentrated in the same spot).
- dom0 10y agoNope, but processors, especially larger ones, have pretty advanced power and clock management which allows them to deal with power envelope and thermal envelope constraints. E.g. the two clocking and core voltage ladders in Xeon E5/E7 for AVX vs. non-AVX code. (Though this particular example is a bit of a sledge-hammer approach).