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I wonder how many servers are currently CPU-bound? I've always been I/O bound (interchange that with memory-bound, depending on how much you would like to spend
by carbocation 16y ago
I wonder how many servers are currently CPU-bound? I've always been I/O bound (interchange that with memory-bound, depending on how much you would like to spend on memory).
- matthavener 16y agoConsidering there is 8 meg of cache for all the cores, this must be for CPU-bound tasks only
- ehnus 16y agoThe article says that it has 8mb of cache per core, shared by four hardware threads.
- pcarmichael 16y agoThat's 400MB of cache on the die, which seems highly unlikely.
- pjscott 16y agoThat would be far more remarkable than putting 50 cores on the die. It would be cause for riotous celebration.
- 1amzave 16y ago> riotous celebration Well, maybe. There are diminishing returns on increasing cache sizes (you solve the capacity misses but don't really deal with compulsory and conflict misses)...though it would be impressive an impressive feat of process technology. The closest to that amount at the moment I believe is IBM's Power 7, which has a 30MB on-die L3 implemented in eDRAM.
- pjscott 16y agoThe article is mistaken; the 8 MB is shared between the 50 cores. There's some speculation that it might be a Non-Uniform Cache Access architecture, where local parts of the shared cache are faster to read/write than other parts. If so, that would certainly be an impressive step. A better article is here: http://www.channelregister.co.uk/2010/06/01/intel_knights_co_processor/print.html http://www.channelregister.co.uk/2010/06/01/intel_knights_co...
- wmf 16y agoMany HPC servers are CPU-bound.
- Tamerlin 16y agoTrue, but commercially speaking they're the minority.
- xtacy 16y agoEven if servers are I/O bound, this setup is almost like crunching 50 machines into one; applications will have lower latency access to data stored on larger memory.
- rbanffy 16y agoIt's like crunching 50 CPUs on top one memory bus. Even if there are, say, 5 buses (and a thousand pins for them), that's still 10 cores per bus. Did they say how many threads per core? I suspect it will be like having 50 286s in the same box...